Applying 5 V to 3.3 V output pins

Question

I have a 3.3 V microcontroller pin (not 5 V tolerant) with an external 10 kΩ pull-up resistor. By mistake, the external pull-up resistor was connected to 5 V. As I understand it, the only thing that protects the pin from burning is its protection diode.

If the pin is declared as input, the current path will be 5 V -> pull-up resistor -> pin -> protection diode -> 3.3 V and on the MCU pin there will be 3.3 V + Vdiode.

What is the current path when the pin is declared as a push-pull output and the output level is set to high? What is the voltage level on the microcontroller pin? What is the voltage level when the pin is set to low?

Microcontroller is STM32F103C6T6, and pin is PB5

Answer 1

If you pulled up with 10k, nothing really bad happens as the current will be limited by the resistor.

Specifically, with the pin at its high-Z state:

• I/O pin will bias to about 3.3V + 1 Schottky protection diode drop (0.3V), so about 3.6V.
• Current will be about (5V-3.6V)/10k, so about 140uA.

If pin is driven output-high, the high-side p-FET will conduct taking the 10k pullup close to Vdd (3.3V).

The I/O voltage is therefore limited to within Absolute Maximum ratings, so the part will not suffer damage. Nonetheless, it's something you should fix.

This ST document spells out some of this detail. For most 3.3V I/O, the max voltage is Vdd+0.3V (which implies a Schottky protection diode.) See section 5.1.2, and also note that 'TT' and 'FT' pins tolerate no injected current at all to Vdd. So, this contradicts my own experience with typical 3.3V pads that allow for at least some conduction of the upper diode before Bad Things Happen. Anyway, that's what they said.

If your signal needs to be a 5V open collector style, you can employ a level shifter using a number of techniques. If it's an output, a FET like a BSS138 is ideal.

A thing you need to watch out for is power supply sequence. If 5V comes on before 3.3V then the part can be 'phantom powered' via the I/O pin, leading to unexpected power on / power off behavior.

Answer 2

The voltage on the pin will simply be (very close to) 3.3 V or 0 V (depending on whether it is set low or high). The remaining voltage is simply dropped across the pull up resistor, and the current path is from 5 V, through the resistor, through one of the MOSFETs to either \$V_{DD}\$ or \$V_{SS}\$ depending on the pin state.

Answer 3

When the pin is driving low, all is well. At any other time, the internal protection diode will likely be forward biased with current flowing into the GPIO pin by way of the 10 k pullup. Whether this will cause damage is hard to say. The datasheet may list allowable current in this condition. Or it may not.

You can probably fix this satisfactorily by putting an external 20 k pulldown on the IO pin or putting Schottky diode from the GPIO to the 3.3 V rail powering the processor. These should be adequate fixes for the problem.

Another solution which is more of a half-way solution would be to increase the value of the pullup resistor to 100 k or even more. This may limit the current to a value that does not cause damage to the GPIO.

From a practical perspective, I doubt that the GPIOs will instantly go bad on every board. Most likely, if you have 5 or 10 boards used around the lab, they will all continue to work for a long time. But I would not let this design get out into the wild as-is unless you can verify definitively that the GPIO will tolerate it.