Emissions issue with H-Bridge driving piezo transducers

Question

I have the following block in a PCB design:

This drives a ~ 5W piezo transducer at 113KHz. The functionality of the system is great, nothing heats up at all. The issue is when I did a quick pre-compliance conducted emissions test using a DC LISN:

If I remove the piezo, the emissions improve, but still are pretty terrible:

I have tried using a RC snubber in parallel with the piezo, no real difference. I tried a few different R values in parallel with the piezo, marginal improvement depending on the value. Adding a 220uF electrolytic cap to the 24V rail helped by ~ 2 - 5dBuV across all frequencies. I tried adjusting gate resistors, the larger the value, the worse the emissions.

I know that I can throw a PI filter on the input 24V supply to solve this issue, but with how horrible the emissions are, I feel like that is a bit of a "bandaid" fix. The fact that the larger gate resistor made this worse makes me think that even with the max deadband on the H-bridge driver, that there is a slight shoot-through issue, but I'm not sure. I also can't just put hundreds and hundreds uF of capacitance.

Any thoughts of what I could try to limit the emissions directly?

EDIT: I am directly measuring the input 24VDC using a 5uH LISN by Tekbox.

Answer 1

Your layout can use improvement.

• The FET bypass capacitors (C13, C15) are diving in to the ground plane. This means you have large glitch current (current spikes at the switching edges) running in your ground plane which can cause EMC issues.
• The positioning of your FETs create a large area current loop in conjunction with the FET bypass capacitors. Again, not optimal regarding EMC.

The following image is how I normally build H-bridge amplifiers for 10kW pulse systems. This is half of the H-bridge. Q1 is the upper FET, Q2 is the lower FET, C8 is the FET bypass capacitor. Note that the FET bypass capacitor is connected to Q1's drain and Q2's source directly on surface copper pours. This minimizes parasitic inductance. There are plane layers for the +24V and ground. This arrangement reduces glitch current from flowing in to the power planes and minimizes the loop area.

Consider using a ferrite bead on the 24V power line as part of a PI filter. This will probably improve the situation greatly as this will reduce the switching current glitches on the power line. You also need a few hundred microfarads (use multiple capacitors in parallel) on both sides of the PI filter. Use good quality capacitors rated for switching power supplies. You may need to de-Q the ferrite bead with a 10 to 20 ohm resistor across the ferrite bead. Ferrite beads can form an L-C circuit with the bypass capacitors and ring when hit with current spikes.

Check for cross conduction (hard to do on these types of amplifiers). You state emissions got worse when you increased the gate resistance which is a sign of cross-conduction. You would need to redesign the gate drive scheme (independent gate signals that you can adjust switching parameters) to ensure you don't have cross-conduction.

Consider inserting a tuning inductor in series with the output. If chosen right, the inductor will cancel out the capacitive reactance giving you a nearly resistive impedance. Driving a piezo transducer directly will give a current spike at the switching edges since the transducer looks like a capacitor (transducer is a complex impedance device that is frequency dependent).

Consider using a 100nF capacitor for one of your FET bypass capacitors. It will have better characteristics at higher frequencies.